zeroRISC delivers a synthesizable RTL core — DICE attestation chain, OTP-backed lifecycle controller, fault-injection countermeasures — that OEM silicon architects drop directly into tape-out. Not a finished SoC, not a hosted service: a hard IP block your design team owns from RTL to GDS.
OEM silicon architects integrating security into SoC designs face a grim choice: build a boot ROM and attestation chain from scratch (18–24 months, FIPS audit process alone) or source an unaudited soft-IP block that will fail certification review.
Neither is acceptable for production silicon.
See IP Core DetailszeroRISC solves this with a pre-certified, hardened OpenTitan root-of-trust block — tape-out ready, attestation chain included.
Gate-level Verilog/SystemVerilog. Foundry-agnostic. Validated on TSMC 28nm, GF 22FDX, and SMIC 40nm node libraries.
DICE-compliant certificate chain. Device-unique identity provisioned at manufacturing. Boot-stage certificates verifiable end-to-end.
Designed against FIPS 140-3 Level 3. Cryptographic module validation documentation included in the license package. Eliminates the 18–24 month audit runway your team would otherwise need to budget.
OTP-backed state machine: DEV → PROD → LOCKED → RMA → EOL. Tamper-evident transitions with HMAC-authenticated commands.
Physical side-channel countermeasures: redundant logic paths, glitch detectors, randomized pipeline stalls, power analysis hardening.
AHB/AXI4-Lite bus interface, integration guide, DFT insertion hooks, synthesis constraints, and DV testbench infrastructure.
Dominic Rizzo and the zeroRISC team spent years inside hardware security research before founding zeroRISC in Cambridge, MA in 2022. The company's founding insight: the open-source OpenTitan root-of-trust specification is technically superior to proprietary alternatives — but OEM adoption stalls because bringing it through FIPS 140-3 certification is a multi-year engineering project.
zeroRISC does that once and ships the result as licensable RTL.
FIPS 140-3 Level 3 imposes strict physical security requirements that most silicon IP vendors skip. We explain what the certification actually requires and how a pre-certified RTL block collapses the 18-month audit timeline.
DICE establishes hardware-rooted identity through a layered certificate chain. We trace the full derivation from Unique Device Secret through CDI_0, CDI_1, to the application certificate.
The lifecycle state machine is the backbone of silicon security. Getting DEV-to-PROD locking wrong means field devices remain debuggable.
Request a datasheet or schedule a technical briefing with our IP integration engineers.